1. Field of the Invention
The present invention relates to a digital filter, and particularly, to an improved digital filter capable of advantageously completing a filter operation through a convolution using a filter coefficient used in each stage of multi-stage digital filters and previously stored in a ROM (Read Only Memory).
2. Description of the Conventional Art
Conventionally, as shown in FIG. 1, a multi-stage digital filter, such as a two-stage digital filter, includes a control unit 10 for controlling a filtering operation, an input buffer 20 for buffering a digital data inputted thereto, a first stage filter 30 for filtering a data outputted from the input buffer 20, and a second stage filter 40 for filtering a data outputted from the first stage filter 30.
The first stage filter 30 includes a RAM (Random Access Memory) 31 for storing a data outputted from the input buffer 20, a ROM 33 for storing a coefficient of the first stage filter 30, an addressing unit 32 for addressing a filter coefficient stored in the ROM 33, and a multiplying and accumulating unit 44 each for convoluting the data outputted from the RAM 31 and the ROM 33.
The second stage filter 40 is directed to receive a data outputted from the first stage filter 30 and to receive a control signal of the control unit 10 and has the same construction as in the first stage filter 30 that is, a RAM 41, an addressing unit 42, a ROM 43, and a multiplying and accumulating unit 44.
The operation of the conventional two stage digital filter will now be described.
To begin with, the control unit 10 controls the first stage filter 30 to be active when the second stage filter 40 is not active and controls the first stage filter 30 not to be active when the second stage 40 is active.
In addition, when a digital data is inputted to the input buffer 20, the input buffer 20 outputs the data inputted thereto to the RAM 31 in accordance with a control signal of the control unit 10. The RAM 31 stores the data inputted thereto in accordance with the control signal and outputs the stored data to the multiplying and accumulating unit 34. At this time, the addressing unit 32 outputs an address of a corresponding filter coefficient to the ROM 33, and the ROM 33 outputs the address of the corresponding filter coefficient to the multiplying and accumulating unit 34. Thereafter, the multiplying and accumulating unit 34 multiplies the data each outputted from the RAM 31 and the ROM 33, accumulates the multiplied data and then outputs the accumulated data to the second stage filter 40.
Thereafter, the second stage filter 40 performs the same operation as the first stage filter 30.
However, the conventional two stage digital filter requires twice the occupying volume of a single stage digital filter when performing two convolutions. In addition, when a feed back section is adapted to reduce the occupying volume, the filtering speed becomes slow because the control operation is performed through more complicated methods, and because a time sharing is required at the time of the operation of each element.
In addition, when the two stage digital filter is activated as a low pass filter LPF or a high pass filter, the filter coefficient of each stage may be combined. However, a two stage digital filter is activated as an interpolation filter, in which a sampling ratio of an output data varies, and a filter coefficient of each stage may not be combined to one coefficient using a conventional convolution because a corresponding hardware related to a varied sampling ratio is provided between the first and second stage filters.